A processing node or core in a computing system may be placed in any of multiple power states, also referred to as C-states, during operation, where the particular power state is characterized by associated clock and/or power gating. During transitions from one power state to another, secret data (e.g. central processing unit (CPU) cache information that may contain core architectural state information) may be susceptible to attack by one or more unauthorized third parties. Typically, the decision to transition the processing node between power states is made by the trusted operating system (OS) and/or associated microcode. In some instances, every state resume or request to enter an idle power state originating from the operating system is treated as trusted and therefore initiates a corresponding power state change.
With such legacy computing systems, if an unauthorized third party obtains administrator rights to the microcode or operating system, it follows that each may be susceptible to unauthorized manipulation that may hamper the performance of the processing node. For example, because entry and exit from a power state takes significant time to complete, if a third party is able to request a high number of power state changes in a relatively short time period, the performance of the processing node subject to the power state changes may become significantly degraded. Furthermore, secret information may be transferred to off-processor memory when certain power state changes occur. Thus, if an untrusted third party were able to manipulate the operating system or microcode to strategically initiate power state change requests, the third party may be able to predictably recover the secret data.
Therefore, a need exists for methods and systems to provide improved monitoring and secure control during a power state change of the processor to thereby reduce the likelihood of a security breach.